What is the recommended power supply voltage for TTL series integrated circuits?
What logic state do the inputs of a TTL device assume if they are left open?
What level of input voltage is a logic "high" in a TTL device operating with a positive 5-volt power supply?
What level of input voltage is a logic "low" in a TTL device operating with a positive 5-volt power-supply?
Which of the following is an advantage of CMOS logic devices over TTL devices?
Why do CMOS digital integrated circuits have high immunity to noise on the input signal or power supply?
In Figure E6-5, what is the schematic symbol for an AND gate?

In Figure E6-5, what is the schematic symbol for a NAND gate?

In Figure E6-5, what is the schematic symbol for an OR gate?

In Figure E6-5, what is the schematic symbol for a NOR gate?

In Figure E6-5, what is the schematic symbol for the NOT operation (inverter)?
